95
XMEGA A [MANUAL]
8077I–AVR–11/2012
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 5:0 – CALB[5:0]: DFLL Calibration bits
These bits hold the part of the oscillator calibration value that is used to select the oscillator frequency. A factory-
calibrated value is loaded from the signature row of the device and written to this register during reset, giving an oscillator
frequency approximate to the nominal frequency for the oscillator. These bits are not changed during automatic run-time
calibration of the oscillator. The bits cannot be written when the DFLL is enabled. When calibrating to a frequency
different from the default, the CALA bits should be set to a middle value to maximize the range for the DFLL.
7.11.4 COMP0 – DFLL Compare register 0
The COMP0 register represent the frequency ratio between the oscillator and the reference clock. The initial value for
this register is the ratio between the internal oscillator frequency and a 32.768kHz reference.
Bit 7:0 – COMP[7:0]: Compare value byte 0
These bits hold byte 1 of the 16-bit compare register.
7.11.5 COMP1 – DFLL Compare register 1
The COMP1 and COMP2 register pair represent the frequency ratio between the oscillator and the reference clock. The
initial value for these registers is the ratio between the internal oscillator frequency and a 1.024kHz reference.
Bit 7:0 – COMP[15:8]: Compare value byte 1
These bits hold byte 1 of the 16-bit compare register.
Bit
7
654
3210
+0x04
COMP[7:0]
Read/Write
R/W
Initial Value
Bit
7
6543
210
+0x05
COMP[18:8]
Read/Write
R/W
Initial Value
0
0000
000
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